Master and PhD thesis:
PhD thesis, “Plataforma modular e interfaces genéricas de transductores para redes de sensores inalámbricas“, by Jorge Portilla, May 2010.
Master thesis, “Plataforma de Integración Hardware-Software para Testbed de Redes de Sensores Inalámbricas“, by Gabriel Noe Mujica, March 2012.
Master thesis,”ESTUDIO DE BANDA DE FRECUENCIAS SUB-GHz PARA REDES DE SENSORES INALÁMBRICAS E IMPLEMENTACIÓN EN PLATAFORMA MODULAR“, by, Mariana Molina Matute, March 2011.
Final degree project, “DISEÑO Y DESPLIEGUE DE UNA RED DE SENSORES INALÁMBRICA. APLICACIÓN PARA EL CONTROL MEDIOAMBIENTAL EN LA INDUSTRIA ALIMENTARIA“, by Juan Valverde, September 2010.
Master thesis,”MODELADO PARA SIMULACIÓN DE REDES DE SENSORES INALÁMBRICAS PREDESPLIEGUE BASADO EN VISUALSENSE“, by Victor Rosello, September 2009.
Master Thesis, “FPGA-BASED WIRELESS SENSOR NODE ARCHITECTURE FOR HIGH PERFORMANCE APPLICATIONS“, by Juan Valverde, April 2012.
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ARTICLES IN PROCEEDINGS AND JOURNALS
– M. Lombardo, J. Camarero, J. Valverde, J. Portilla, E. de la Torre, T. Riesgo, “Power Management Techniques in an FPGA-Based WSN Node for High Performance Applications” in International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) 2012.
J. Valverde, A. Otero, M. Lopez, J. Portilla, T. Riesgo, “Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks“, in Sensors 2012, 12, 2667-2692.
– J. Valverde, V. Rosello, G. Mujica, J. Portilla, A. Uriarte, T. Riesgo, “Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory“, in International Journal of Distributed Sensor Networks, 2012, 12 pages, doi:10.1155/2012/638067.
– V. Rosello, J. Portilla, T. Riesgo, “Ultra Low Power FPGA-Based Architecture for
Wake-up Radio in Wireless Sensor Networks“, in Proceedings of the IECON 2011, pp. 3695 – 3700, Melbourne, Australia, November 2011.
– J. Portilla, A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, and P. Langendörfer, “Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors“, International Journal of Distributed Sensor Networks, Volume 2010 (2010), Article ID 740823, 12 pages.
– Y. E. Krasteva. J. Portilla, E. de la Torre, T. Riesgo, “Embedded Run-time Reconfigurable Nodes for Wireless Sensor Networks Applications“, IEEE Sensors Journal, to be published during 2011.
– V. Rosello, J. Portilla,Y. E. Krasteva, T. Riesgo, “Wireless sensor network modular node modeling and simulation with VisualSense“, in Proceedings of the IECON 2009, pp. 2685 – 2689, Porto, Portugal, November 2009.
J. Portilla, T. Riesgo, A. Abril, A. de Castro, “Rapid prototyping for multi-application sensor networking“, 12 November 2007, SPIE Newsroom. DOI: 10.1117/2.1200711.0851
– J. Portilla, A. de Castro, E. de la Torre, T. Riesgo, “A Modular Architecture for Nodes in Wireless Sensor Networks”, Journal of Universal Computer Science (JUCS), vol. 12, nº 3, pp. 328 – 339, March 2006.
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POSTERS AND DEMOS IN CONFERENCES
– V. Rosello, J. Portilla, T. Riesgo, “Poster Abstract: Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA”, in Poster and Demo Proceedings of the EWSN 2012, pp. 88 – 89, Trento, Italy, February 2012. [PosterAbstract] [Poster]
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